Flash memory, which is a typical example of nonvolatile semiconductor memory device, is rapidly expanding its market as a memory unit for small-sized portable information devices such as cellular phones, digital still cameras, etc., as it is handy to carry, shock-proof and also capable of electrical bulk erasing on board.
This flash memory, as for instance illustrated in FIG. 18, usually consists of memory cells M which store data and MOS field effect transistors P constituting peripheral circuits for selecting the programming/erasing or read bits or generating a necessary voltage in the chips.
Unitary memory cell M comprises a set of MOS field effect transistors each consisting of a silicon (Si) substrate 201 having source and drain diffusion layers (not shown), a P well 204a formed on said Si substrate, a floating gate 207 and a control gate 209 both of which comprise mainly a polycrystalline Si film, an interpoly dielectric film 208 separating said gates 207 and 209, and a tunnel dielectric film 206 separating said floating gate 207 and P well 204a, and a plurality of such memory units are arranged as a matrix. As the interpoly dielectric film separating the floating and control gates of each memory cell, there is usually used a so-called ONO film which is a stacked film comprising a silicon nitride (Si3N4) film sandwiched between the SiO2 films, said ONO film being higher in permittivity and smaller in leakage current than the SiO2 film.
Peripheral circuit P consists of a combination of MOS field effect transistors each comprising a P well 204b and an N well 205 formed in an Si substrate 201, source and drain diffusion layers 212a and 212b, and a gate electrode 211 mainly comprising a polycrystalline Si film formed on the well with the interposition of a gate insulating film 210. Gate insulating film 210 usually comprises a SiO2 film formed by thermal oxidation method.
Each unitary memory cell M and peripheral circuit transistors P are usually separated by an isolation region 202 comprising a thick oxide film. The quantity of charge accumulated in the floating gate is controlled by biasing the positive or negative voltage generated by the peripheral circuit to the control gate 209, and the threshold voltage of the memory cell transistors is varied accordingly to thereby discriminate “0” and “1” of data.
However, increase of density of said nonvolatile semiconductor memory device has given rise to the new problems over the MOS transistors P for peripheral circuits and the memory cells M.
One of such problems is deterioration of characteristics and reliability of the MOS transistors for peripheral circuits due to degradation of the gate oxide film.
In flash memory, a high voltage, such as, for example, 18 V, is applied to the word line at writing/erasing. For the MOS transistors for peripheral circuits exposed to such high voltage, the gate oxide film thickness is increased to, for instance, around 25 nm so that the film can withstand such high voltage. However, in case the shallow groove isolation method is applied in place of the conventional selective oxidation method (LOCOS) for isolation between the peripheral MOS transistors for the purpose of miniaturization of the elements, if the thick (such as 25 nm) gate oxide film is formed by the thermal oxidation method, there arises a situation in which the thickness of the gate oxide film adjacent to the shallow groove isolation region becomes excessively small in comparison with the active region. This gives rise to some serious problems such as “kink” of current-voltage characteristics of the MOS transistors and lowering of breakdown voltage of the gate oxide film.
The second problem is difficulty in thinning of the interpoly dielectric film of the memory cells M which is essential for the reduction of programming voltage.
The voltage Vfg applied to the floating gate for the programming/erasing operation of the flash memory is given by the following equation:Vfg=C2·Vcg/(C1+C2)  (1)wherein Vcg is voltage applied to the control gate, and C1 and C2 are capacitance of the tunnel dielectric film and the interpoly dielectric film, respectively. In order to transfer the voltage applied to the control gate efficiently to the floating gate to reduce the programming voltage, it is effective to increase C2, namely to make thinner the interpoly dielectric film. However, in the case of the “ONO film”, i.e. a stacked film comprising a silicon nitride (Si3N4) film sandwiched between the SiO2 films, which has been widely used in the art, if the thickness of the SiO2 film on each side of the laminate is made 5 nm or less, there would arise the problem that the charge accumulated in the floating gate might leak out to the control gate, that is, actualization of so-called retention degradation. Also, when the SiO2 film on the upper side of the laminate is made 5 nm in thickness, it is necessary to deposit the Si3N4 film to a thickness of around 10 nm or greater for preventing oxidation of the polycrystalline Si layer on the lower side. Thus, the limit of possible reduction of thickness of the ONO film was around 15 nm in terms of effective oxide thickness.
JP-A-10-242310 discloses a technique for reducing the programming voltage by lessening the film thickness by applying a nitrogen-introduced single-layer CVD SiO2 film as the interpoly dielectric film in place of the conventional ONO film.
However, when the gate oxide film of the peripheral circuit MOS transistors was formed by the thermal oxidation method after forming the interpoly dielectric film, as commonly practiced in manufacture of the conventional flash memories, there would arise the problem that the highly doped floating gate polycrystalline Si be oxidized thickly because the single-layer CVD SiO2 film has no oxidation resistance unlike the ONO film. Therefore, development of a reliable method for forming a gate oxide film of the peripheral circuit MOS transistors when using a single-layer CVD SiO2 film as the interpoly dielectric film for memory cell was essential.
The third problem is the increase of the number of the steps in the production process.
In the conventional flash memory production process, the tunnel dielectric film 206 of memory cells, their interpoly dielectric film 208 and the gate insulating film 210 of peripheral circuit MOS transistors have been formed severally in succession, so that the process involved many steps and this has been an obstacle to the effort for cost reduction. Recently, an idea of the techniques for making two type thickness of the gate oxide film of MOS transistors in the peripheral circuit region is proposed for attaining further enhancement of programming/erasing speed and read speed of the flash memory. It is considered that the simplification of the flash memory production process will become an important subject for study in the art.
The above-said three problems are closely associated with each other from the viewpoint of formation of interpoly dielectric films of memory cells and gate oxide film of peripheral circuit MOS transistors, and for the solution of these problems, the development of a novel nonvolatile semiconductor memory device and its production process has been required.
Accordingly, an object of the present invention is to make highly reliable the gate oxide film of peripheral circuit MOS transistors of nonvolatile semiconductor memory device and to improve its transistor characteristics.
Another object of the present invention is to provide a process for forming the interpoly dielectric film and the gate oxide film of MOS transistors in the peripheral circuit region that accord with the miniaturization and low-voltage operation of nonvolatile semiconductor memory device.
Still another object of the present invention is to simplify the production process of nonvolatile semiconductor memory device.